In recent years there has been an increased requirement for high lead count interconnect devices, especially for high density electrical components such as integrated circuits, multichip modules, etc. In recent years the packaging of integrated circuits (ICs) has evolved from conventional devices such as the dual in-line package (DIP) to a variety of devices such as surface mounted packages. This evolution has led to the need for further advanced interconnect devices to connect the ICs to other circuitry. Various approaches have been proposed and used to effect such interconnection, such as wire bonding and tape automated bonding (TAB) products.
As this field of technology has developed, the requirements for the number of leads to connect the IC to external circuitry has increased. That is, there is a growing requirement for interconnect devices that are sometimes referred to as high lead count devices. There is a need in the art for high lead count in the range of 300 or more. As the lead count increases, the requirements for the interconnect device become more difficult. The problems are further compounded or complicated by requirements for increased switching speed and increased switching current, all of which combine with high lead count to cause serious noise problems and create or present the need for extremely low inductance decoupling.
Prior application Ser. No. 352,112, filed May 15, 1989 (now U.S. Pat. No. 4,995,941, the entire disclosure of which is incorporated herein by reference) and assigned to the assignee hereof, disclosed apparatus and a method for an interconnect device having fine lead widths, fine lead spacing, close control of input/output (I/O) line width and also incorporating a voltage (power or ground) plane with via interconnects between the voltage plane and selected I/O leads. Copending application Ser. No. 601,927 filed Oct. 23, 1990 for Multilayer Interconnect Device and Method of Manufacture Thereof, now U.S. Pat. No. 5,053,921, and assigned to the assignee hereof, expands on the subject matter of U.S. Ser. No. 352,112 to achieve an interconnect device having both power and ground planes connected by vias to selected I/O leads.
As the requirements grow for high lead count interconnect devices, the factors of size of the interconnect device and lead spacing and low inductance decoupling become more critical. This is particularly true where, as was the case in the prior art, a large percentage (typically up to 30%) of the I/O leads of a TAB interconnect device are devoted to ground and power supply to the IC. That means, of course, that for each I/O lead dedicated to power or ground, there is one less lead available for I/O signal transmission. The result is that if size is the controlling factor, one must settle for an interconnect device whose I/O signal lead capacity is reduced by the number of leads that must be dedicated to ground and power supply. Conversely, if signal carrying capacity is the controlling factor, one must use an interconnect device of a size large enough to accommodate all of the signal I/O lines and all of the I/O lines dedicated to ground and power supply. This often results in the need to increase the size (and the manufacturing cost) of the IC die (because of the need to increase the number of I/O pads on the die) and also results in using up valuable "real estate" on the circuit board of which the IC is a part.
In addition to the above, many high lead count ICs have requirements for interconnect devices with impedance control to reduce mismatched impedance of signal lines. Also, with fine pitch of leads, signal crosstalk may become a problem. Similarly, there are requirements for high lead count interconnection devices for other electronic components, such as high density multichip modules, to interconnect the electronic components to other circuit components such as a printed circuit board. Such high lead count interconnect devices may have problems and requirements similar to those discussed above.